Junction-to-ambient thermal resistance (θJA
參數(shù)資料
型號(hào)： A54SX08A-1TQ144I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 35/108頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 144-TQFP
標(biāo)準(zhǔn)包裝： 60
系列： SX-A
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 113
門數(shù)： 12000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
SX-A Family FPGAs
2- 12
v5.3
Theta-JA
Junction-to-ambient thermal resistance (θJA) is determined under standard conditions specified by JESD-51 series but
has little relevance in actual performance of the product in real application. It should be employed with caution but is
useful for comparing the thermal performance of one package to another.
A sample calculation to estimate the absolute maximum power dissipation allowed (worst case) for a 329-pin PBGA
package at still air is as follows. i.e.:
EQ 2-11
The device's power consumption must be lower than the calculated maximum power dissipation by the package.
The power consumption of a device can be calculated using the Actel power calculator. If the power consumption is
higher than the device's maximum allowable power dissipation, then a heat sink can be attached on top of the case or
the airflow inside the system must be increased.
Theta-JC
Junction-to-case thermal resistance (θJC) measures the ability of a device to dissipate heat from the surface of the chip
to the top or bottom surface of the package. It is applicable for packages used with external heat sinks and only
applies to situations where all or nearly all of the heat is dissipated through the surface in consideration. If the power
consumption is higher than the calculated maximum power dissipation of the package, then a heat sink is required.
Calculation for Heat Sink
For example, in a design implemented in a FG484 package, the power consumption value using the power calculator is
3.00 W. The user-dependent data TJ and TA are given as follows:
From the datasheet:
EQ 2-12
The 2.22 W power is less than then required 3.00 W; therefore, the design requires a heat sink or the airflow where the
device is mounted should be increased. The design's junction-to-air thermal resistance requirement can be estimated
by:
EQ 2-13
θ
JA
= 17.1°C/W is taken from Table 2-12 on page 2-11
TA
= 125°C is the maximum limit of ambient (from the datasheet)
Max. Allowed Power
Max Junction Temp
Max. Ambient Temp
–
θ
JA
------------------------------------------------------------------------------------------------------------
150
°C 125°C
–
17.1
°C/W
----------------------------------------
1.46 W
==
=
TJ = 110°C
TA = 70°C
θ
JA = 18.0°C/W
θ
JC = 3.2 °C/W
P
Max Junction Temp
Max. Ambient Temp
–
θ
JA
------------------------------------------------------------------------------------------------------------
110
°C70°C
–
18.0
°C/W
------------------------------------
2.22 W
==
=
θ
JA
Max Junction Temp
Max. Ambient Temp
–
P
------------------------------------------------------------------------------------------------------------
110
°C70°C
–
3.00 W
------------------------------------
13.33
°C/W
==
=
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參數(shù)描述
A54SX08A-1TQ208 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
A54SX08A-1TQ208A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
A54SX08A-1TQ208B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
A54SX08A-1TQ208I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
A54SX08A-1TQ208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
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