- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4437 > A54SX08-2VQG100I (Microsemi SoC)IC FPGA SX 12K GATES 100-VQFP PDF資料下載
參數(shù)資料
| 型號： | A54SX08-2VQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 9/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SX 12K GATES 100-VQFP |
| 標準包裝： | 90 |
| 系列： | SX |
| LAB/CLB數(shù)： | 768 |
| 輸入/輸出數(shù)： | 81 |
| 門數(shù)： | 12000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-VQFP（14x14） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
SX Family FPGAs
v3.2
1-13
A54SX16P AC Specifications (3.3 V PCI Operation)
Table 1-9
A54SX16P AC Specifications (3.3 V PCI Operation)
Symbol Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCC
1
mA
0.3VCC ≤ VOUT < 0.9VCC
1
–12VCC
mA
0.7VCC < VOUT < VCC
1, 2
–17.1 + (VCC – VOUT)
(Test Point)
VOUT = 0.7VCC
2
–32VCC
mA
IOL(AC)
Switching Current High
VCC > VOUT ≥ 0.6VCC
1
mA
0.6VCC > VOUT > 0.1VCC
1
16VCC
mA
0.18VCC > VOUT > 0
1, 2
26.7VOUT
mA
(Test Point)
VOUT = 0.18VCC
2
38VCC
ICL
Low Clamp Current
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
mA
ICH
High Clamp Current
–3 < VIN ≤ –1
25 + (VIN – VOUT – 1)/0.015
mA
slewR
Output Rise Slew Rate3
0.2VCC to 0.6VCC load
1
4
V/ns
slewF
Output Fall Slew Rate3
0.6VCC to 0.2VCC load
1
4
V/ns
Notes:
1. Refer to the V/I curves in Figure 1-10 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be
one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to
CLK and RST# which are system outputs. “Switching Current High” specification are not relevant to SERR#, INTA#, INTB#,
INTC#, and INTD# which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums
(C and D) are provided with the respective diagrams in Figure 1-10 on page 1-14. The equation defined maxima should be
met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output
driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate
at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet
this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both
maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply
to open drain outputs.
1/2 in. max.
Pin
Output
Buffer
VCC
10 pF
1 k
Ω
1 k
Ω
相關PDF資料 |
PDF描述 |
|---|---|
| A54SX16-2VQG100 | IC FPGA SX 24K GATES 100-VQFP |
| A54SX16-1VQG100I | IC FPGA SX 24K GATES 100-VQFP |
| A1415A-PLG84I | IC FPGA 1500 GATES 84-PLCC |
| A1415A-PL84I | IC FPGA 1500 GATES 84-PLCC |
| A54SX72A-FPQ208 | IC FPGA SX-A 108K 208-PQFP |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08-3BG208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-3BG208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-3BG208M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-3BG208PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08-3FG144 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購，3分鐘左右您將得到回復。