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參數(shù)資料
| 型號： | A49LF040TL-33F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 4兆位的CMOS 3.3Volt只低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 570K |
| 代理商： | A49LF040TL-33F |
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Table 1: Pin Description
A49LF040
PRELIMINARY (August, 2004, Version 0.1)
4
AMIC Technology, Corp.
1. IN=Input, OUT=output, I/O=Input/Output, PWR=Power
Interface
A/A
Mux
Symbol
Pin Name
Type
LPC
Descriptions
A
10
-A
0
Address
IN
X
Inputs for addresses during Read and Write operations in A/A Mux
mode. Row and column addresses are latched by R/C# pin.
I/O
7
-I/O
0
Data
I/O
X
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE# is high.
OE#
Output Enable
IN
X
To control the data output buffers.
WE#
Write Enable
IN
X
To control the Write operations.
MODE
Interface
Configuration Pin
IN
X
X
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, LPC mode is enabled.
This pin must be setup at power-up or before return from reset and
not change during device operation. This pin is internally pulled
down with a resistor between 20-100 K
.
INIT#
Initialize
IN
X
This is the second reset pin for in-system use. INIT# and RST#
pins are internally combined and initialize a device reset when
driven low.
ID[3:0]
Identification Inputs
IN
X
These four pins are part of the mechanism that allows multiple
LPC devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count strapping.
These pins are internally pulled down with a resistor between 20-
100 K
.
GPI[4:0]
General Purpose
Inputs
IN
X
These individual inputs can be used for additional board flexibility.
The state of these pins can be read immediately at boot, through
LPC internal registers. These inputs should be at their desired
state before the start of the PCI clock cycle during which the read
is attempted, and should remain in place until the end of the Read
cycle. Unused GPI pins must not be floated.
TBL#
Top Block Lock
IN
X
To prevent any write operations to the Boot Block when driven low,
regardless of the state of the block lock registers. When TBL# is
high it disables hardware write protection for the top Boot Block.
This pin cannot be left unconnected.
LAD[3:0]
LPC I/Os
I/O
X
I/O Communications in LPC mode.
LCLK
Clock
IN
X
To provide a clock input to the device. This pin is the same as that
for the PCI clock and adheres to the PCI specifications.
LFRAME#
Frame
IN
X
To indicate start of a data transfer operation; also used to abort an
LPC cycle in progress.
RST#
Reset
IN
X
X
To reset the operation of the device
WP#
Write Protect
IN
X
When low, prevents any write operations to all but the highest
addressable block. When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
R/C#
Row/Column Select
IN
X
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
RB#
Ready/Busy#
OUT
X
To determine if the device is busy in write operations. Valid only in
A/A Mux mode.
RES
Reserved
X
Reserved. These pins must be left unconnected.
VDD
Power Supply
PWR
X
X
To provide power supply (3.0-3.6Volt).
VSS
Ground
PWR
X
X
Circuit ground. All VSS pins must be grounded.
NC
No Connection
X
X
Unconnected pins.
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