參數(shù)資料
型號： A49LF040TL-33
廠商： AMIC Technology Corporation
英文描述： 128 x 64 pixel format, LED Backlight available
中文描述： 4兆位的CMOS 3.3Volt只低引腳數(shù)快閃記憶體
文件頁數(shù)： 13/31頁
文件大小： 570K
代理商： A49LF040TL-33
A49LF040
PRELIMINARY (August, 2004, Version 0.1)
12
AMIC Technology, Corp.
to read I/O
7
will produce a ‘0’. Once the internal Erase
operation is completed, I/O
7
will produce a ‘1’. The Data#
Polling is valid after the rising edge of fourth WE# pulse for
Program operation. For Block- or Chip-Erase, the Data#
Polling is valid after the rising edge of sixth WE# pulse. See
Figure 12 for Data# Polling timing diagram. Proper status will
not be given using Data# Polling if the address is in the
invalid range.
Toggle Bit (I/O
6
)
During the internal Program or Erase operation, any
consecutive attempts to read I/O
6
will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# pulse
for Program operation. For Block- or Chip-Erase, the Toggle
Bit is valid after the rising edge of sixth WE# pulse. See
Figure 13 for Toggle Bit timing diagram.
Data Protection
The A49LF040 device provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the
Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The A49LF040 provides the JEDEC approved Software Data
Protection scheme for all data alteration operation, i.e.,
Program and Erase. Any Program operation requires the
inclusion of a series of three-byte sequences. The three-byte
load sequence is used to initiate the Program operation,
providing
optimal
protection
operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of a six-byte load
sequence. The A49LF040 device is shipped with the
Software Data Protection permanently enabled. See Table
11 for the specific software command codes. During SDP
command sequence, invalid commands will abort the device
to Read mode, within T
RC
.
Electrical Specifications
The AC and DC specifications for the LPC Interface signals
(LAD[3:0], LCLK, LFRAME#, and RST#) as defined in
Section 4.2.2 of the
PCI Local Bus Specification, Rev. 2.1
.
Refer to Table 12 for the DC voltage and current
specifications. Refer to the specifications on Table 13 to
Table 22 for Clock, Read/Write, and Reset operations.
Product Identification
The product identification mode identifies the Manufacturer
ID, Continuation ID, and Device ID of the A49LF040. See
Table 9 for detail information.
from
inadvertent
Write
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A49LF040TL-33F 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040TX-33 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49LF040TX-33F 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
A49P21N 制造商:Pentair Technical Products / Hoffman 功能描述:Panel, NEMA 1 White, fits 60.00x25.5/26, Steel
A49P21NG 制造商:Pentair Technical Products / Hoffman 功能描述:Panel, 49.16X21.50 , fits 60.00x25.5/26, Steel
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