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參數(shù)資料
| 型號(hào)： | A45L9332AF |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 32 Bit X 2 Banks Synchronous Graphic RAM |
| 中文描述： | 256 × 32位× 2銀行同步圖形內(nèi)存 |
| 文件頁數(shù)： | 11/55頁 |
| 文件大小： | 1255K |
| 代理商： | A45L9332AF |
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A45L9332A Series
PRELIMINARY
(October, 2001, Version 0.1)
10
AMIC Technology, Inc.
Simplified Truth Table
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DSF DQM A10 A9 A8~A0 Notes
Mode Register Set
Special Mode Register Set
Auto Refresh
L
H
1,2
1,2,7
3
Register
H
X
L
L
L
L
X
OP CODE
H
L
Entry
H
L
L
L
H
L
X
X
3
3
L
H
H
H
Refresh
Self
Refresh
Exit
L
H
H
X
X
X
X
X
X
3
4,5
4,5,9
4
4,6
4,5
Write Per Bite Disable
L
H
Bank Active
& Row Addr. Write Per Bit Enable
Auto Precharge Disable
Read &
Column Addr. Auto Precharge Enable
Auto Precharge Disable
Write &
Column Addr. Auto Precharge Enable
Auto Precharge Disable
Block Write &
Column Addr. Auto Precharge Enable
Burst Stop
Bank Selection
Precharge
Both Banks
H
X
L
L
H
H
X
V
Row Addr.
L
H
L
H
L
H
H
X
L
H
L
H
L
X
V
Column
Addr.
H
X
L
H
L
L
L
X
V
Column
Addr. 4,5,6,9
Column
Addr. 4,5,6,9
4,5
H
X
L
H
L
L
H
X
V
H
X
L
H
H
L
L
X
X
7
8
V
X
L
H
H
X
L
L
H
L
L
X
X
L
H
X
L
H
L
H
H
X
X
H
X
V
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
X
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
X
Entry
H
L
X
X
V
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
H
X
V
X
L
H
H
X
H
X
H
X
No Operation Command
H
X
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note :
1. OP Code : Operand Code
A0~A10 : Program keys. (@MRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
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