參數(shù)資料
型號(hào)： A45L9332AE-7
廠商： AMIC Technology Corporation
英文描述： 256K X 32 Bit X 2 Banks Synchronous Graphic RAM
中文描述： 256 × 32位× 2銀行同步圖形內(nèi)存
文件頁(yè)數(shù)： 6/55頁(yè)
文件大?。?/td> 1255K
代理商： A45L9332AE-7
A45L9332A Series
PRELIMINARY
(October, 2001, Version 0.1)
5
AMIC Technology, Inc.
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Storage Temperature (T
STG
) . . . . . . . . . -55
°
C to +150
°
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Input Capacitance
CI1
CI2
A0 to A9, BA
2
2
4
4
pF
pF
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
DQMi, DSF
DQ0 to DQ15
Data Input/Output Capacitance
CI/O
2
6
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VDD,VDDQ
V
IH
V
IL
V
OH
V
OL
3.0
2.0
-0.3
2.4
-
3.3
3.0
0
-
-
3.6
V
V
V
V
V
VDD+0.3
0.8
-
0.4
Note 1
I
OH
= -2mA
I
OL
= 2mA
Input Leakage Current
I
IL
-5
-
5
μ
A
μ
A
Note 2
Output Leakage Current
I
OL
-5
-
5
Note 3
Output Loading Condition
See Figure 1
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
C
DC1
0.1 + 0.01
μ
F
μ
F
Decoupling Capacitance between VDDQ and VSSQ
C
DC2
0.1 + 0.01
Note:
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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