參數(shù)資料
型號: A43E06321G-95UF
廠商: AMIC Technology Corporation
英文描述: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
中文描述: 為512k × 32位× 2銀行低功耗同步DRAM
文件頁數(shù): 10/46頁
文件大小: 1351K
代理商: A43E06321G-95UF
A43E06321
PRELIMINARY
(July, 2005, Version 0.0)
9
AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
0
(Note 3) (Note 1) (Note 2)
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1 A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
0
0
1
-
1
Interleave
0
0
1
2
2
1
0
0
1
0
2
0
1
0
4
4
1
1
Vendor
Use
Only
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
Note :
1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register).
Extended Mode Register Table
BA
1
A10
All have to be set to “0”
A9
A8
A7
Bank
Up/Down
A6
A5
A4
A3
A2
A1
PASR
A0
Address Bus (Ax)
DS
0
(Note)
Driver Strength
Partial-Array Self Refresh:
Driver Strength
A6
0
0
1
1
A5
0
1
0
1
Driver Strength
Full
3/4
1/2
1/4
A7
A2
A1
A0
Banks to be Self-Refreshed
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
X
0
0
1
1
X
0
1
0
1
X
0
1
0
1
X
All banks (Bank 0, 1)
Reserved
Bank 0
Reserved
Reserved
All banks (Bank 0, 1)
Reserved
One bank (Bank 1)
Reserved
Reserved
Note:
BA must be 1 to select the Extended Mode Register (vs. the Mode Register)
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