參數(shù)資料
型號(hào): A43E06321G-95F
廠商: AMIC Technology Corporation
英文描述: 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM
中文描述: 為512k × 32位× 2銀行低功耗同步DRAM
文件頁數(shù): 33/46頁
文件大?。?/td> 1351K
代理商: A43E06321G-95F
A43E06321
PRELIMINARY (July, 2005, Version 0.0)
32
AMIC Technology, Corp.
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Burst Length = Full Page)
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ’s after burst stop, it is same as the case of
RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
High
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
Row Active
(A-Bank)
: Don't care
RAa
A10/AP
CAa
RAa
WE
QAa3
QAa2
QAa1
QAa4
QAb0
DQM
QAa4
QAa3
QAa1
QAa2
QAb0
QAb1
QAb2 QAb3
DQ
(CL=2)
QAb1
QAb2
QAb3
DQ
(CL=3)
Precharge
(A-Bank)
Read
(A-Bank)
CAb
Read
(A-Bank)
Burst Stop
* Note 1
* Note 1
1
* Note 2
QAa0
QAb4 QAb5
1
QAa0
2
QAb4
QAb5
2
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