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參數(shù)資料
| 型號： | A43E06321 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | Knob, Accessories; Color:Red; External Height:0.27" RoHS Compliant: Yes |
| 中文描述： | 為512k × 32位× 2銀行低功耗同步DRAM |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 1351K |
| 代理商： | A43E06321 |
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A43E06321
PRELIMINARY (July, 2005, Version 0.0)
13
AMIC Technology, Corp.
be taken to make sure that burst write is completed or DQM
is used to inhibit writing before precharge command is
asserted. The maximum time any bank can be active is
specified by t
RAS
(max). Therefore, each bank has to be
precharged within t
RAS
(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when all banks are in idle
state.
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
RAS
(min) and “t
RP
” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst read or burst write by asserting high
on A10/AP. If burst read or burst write command is issued
with low on A10/AP, the bank is left active until a new
command is asserted. Once auto precharge command is
given, no new commands are possible to that particular bank
until the bank achieves idle state.
All Banks Precharge
All banks can be precharged at the same time by using
Precharge all command. Asserting low on
CS
,
RAS
and
WE
with high on A10/AP after both banks have satisfied
t
RAS
(min) requirement, performs precharge on all banks. At
the end of tRP after performing precharge all, all banks are
in idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on
CS
,
RAS
and
CAS
with high on CKE
and
WE
. The auto refresh command can only be asserted
with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by “t
RC
(min)”. The minimum number of clock cycles
required can be calculated by dividing “t
RC
” with clock cycle
time and then rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. All banks will be in the
idle state at the end of auto refresh operation. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 15.6us or a burst of 4096
auto refresh cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
CS
,
RAS
,
CAS
and CKE with high on
WE
. Once the self refresh mode is entered, only CKE state
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
RC
” before the SDRAM reaches idle
state to begin normal operation. Upon exiting the self refresh
mode, AUTO REFRESH commands must be issued every
15.6
μ
s or less as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
Deep Power Down Mode
The Deep Power Down Mode is an unique function on Low
Power SDRAMs with very low standby currents. All internal
voltage generators inside the Low Power SDRAMs are
stopped and all memory data will be lost in this mode. To
enter the Deep Power Down Mode all banks must be
precharged and the necessary Precharged Delay t
RP
must
occur.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A43E06321G-75F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
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| A43E06321G-95F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E06321G-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:512K X 32 Bit X 2 Banks Low Power Synchronous DRAM |
| A43E0632G-75I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Synchronous DRAM |
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