參數(shù)資料
型號(hào)： A42U0616S
廠商： AMIC Technology Corporation
英文描述： 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
中文描述： 100萬(wàn)× 16的CMOS動(dòng)態(tài)RAM與江戶頁(yè)面模式
文件頁(yè)數(shù)： 3/25頁(yè)
文件大?。?/td> 278K
代理商： A42U0616S
A42U0616 Series
PRELIMINARY
(June, 2001, Version 0.0)
2
AMIC Technology, Inc.
Selection Guide
Symbol
Description
-50
-60
-80
Unit
t
RAC
Maximum
RAS
Access Time
50
60
80
ns
t
AA
Maximum Column Address Access Time
25
30
40
ns
t
CAC
Maximum
CAS
Access Time
13
15
20
ns
t
OEA
Maximum Output Enable (
OE
) Access Time
13
15
20
ns
t
RC
Minimum Read or Write Cycle Time
84
104
134
ns
t
PC
Minimum EDO Cycle Time
20
25
35
ns
Functional Description
The A42U0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column address.
RAS
and
CAS
are used to strobe the row address and the
column address, respectively.
The A42U0616 has two
CAS
inputs:
LCAS
controls I/O
0
-
I/O
7
, and
UCAS
controls I/O
8
-
I/O
15
,
UCAS
and
LCAS
function in an identical manner to
CAS
in that either will
generate an internal
CAS
signal. The
CAS
function and
timing are determined by the first
CAS
(
UCAS
or
LCAS
) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using
LCAS
and
UCAS
separately.
A Read cycle is performed by holding the WE signal high
during RAS/
CAS
operation. A Write cycle is executed by
holding the WE signal low during RAS /
CAS
operation;
the input data is latched by the falling edge of WE or
CAS
, whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS,
CAS
,
WE and OE controlling the in direction.
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS
. While holding RAS low,
CAS
can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42U0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the
CAS
precharge
time (t
cp
). Since data can be output after
CAS
goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS
high. Memory cell data will retain its correct state by
maintaining
power
and
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 μs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and
CAS
.
It is recommended that RAS and
CAS
track with VCC or
be held at a valid V
IH
during Power-On to avoid current
surges.
accessing
all
1024(1K)
相關(guān)PDF資料
PDF描述
A42U0616S-50 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616S-60 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616S-80 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616V 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616V-50 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42U0616S-50 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616S-60 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616S-80 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
A42U0616V 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
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