![](http://datasheet.mmic.net.cn/160000/A40MX04-1PL44IX79_datasheet_8356750/A40MX04-1PL44IX79_11.png)
40MX and 42MX FPGA Families
v6.1
1-5
Figure 1-7 Clock Networks of 42MX Devices
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 Quadrant Clock Network of A42MX36 Devices
CLKB
CLKA
From
Pads
Clock
Drivers
CLKMOD
CLKINB
CLKINA
S0
S1
Internal
Signal
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Quad
Clock
Modul
QCLKA
QCLKB
*QCLK1IN
S0 S1
QCLK1
Quad
Clock
Modul
*QCLK2IN
S0 S1
QCLK2
Quad
Clock
Modul
QCLKC
QCLKD
*QCLK3IN
S0
S1
QCLK3
Quad
Clock
Modul
*QCLK4IN
S0
S1
QCLK4