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  • 參數(shù)資料
    型號: A40MX04-2PL68I
    廠商: Microsemi SoC
    文件頁數(shù): 110/142頁
    文件大?。?/td> 0K
    描述: IC FPGA MX SGL CHIP 6K 68-PLCC
    標(biāo)準(zhǔn)包裝: 19
    系列: MX
    輸入/輸出數(shù): 57
    門數(shù): 6000
    電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 68-LCC(J 形引線)
    供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
    40MX and 42MX FPGA Families
    Re vi s i on 11
    1-3
    A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the
    device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that
    found in CPLD architectures (Figure 1-4). The D-module allows A42MX24 and A42MX36 devices to
    perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the D-module
    has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an
    output pin, and can also be fed back into the array to be incorporated into other logic.
    Dual-Port SRAM Modules
    The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or
    asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as
    32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width
    and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5.
    The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports.
    Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0],
    respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5
    and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks
    (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The
    SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to
    segmented vertical routing tracks.
    The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications
    requiring FIFO and LIFO queues. The ACTgen Macro Builder within Microsemi's Designer software
    Figure 1-3
    42MX S-Module Implementation
    CLR
    Up to 7-Input Function Plus D-Type Flip-Flop with Clear
    Up to 4-Input Function Plus Latch with Clear
    D0
    D1
    S
    Y
    D
    Q
    GATE
    CLR
    OUT
    Up to 8-Input Function (Same as C-Module)
    D00
    D01
    D10
    D11
    S1
    S0
    Y
    OUT
    Up to 7-Input Function Plus Latch
    D00
    D01
    D10
    D11
    S1
    S0
    Y
    OUT
    GATE
    D
    Q
    D00
    D01
    D10
    D11
    S1
    S0
    Y
    D
    Q
    OUT
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