II Revision 13 I/Os Per Package 1 ProASIC3 Devices A3P" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P250-1PQ208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 112/220闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 250K 208-PQFP
鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� A3P250,A3P125 Wire Change 12/jan/2012
妯欐簴鍖呰锛� 24
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 151
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�鐣跺墠绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�
ProASIC3 Flash Family FPGAs
II
Revision 13
I/Os Per Package 1
ProASIC3
Devices
A3P0152
A3P030
A3P060
A3P125
A3P250 3
A3P400 3
A3P600
A3P1000
Cortex-M1
Devices
M1A3P250 3,5
M1A3P400 3
M1A3P600
M1A3P1000
Package
I/O Type
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
QN48
鈥�
34
鈥�
鈥撯€撯€�
鈥撯€�
QN68
49
鈥�
QN1325
鈥�
818084
87
19
鈥�
CS121
鈥�
96
鈥�
鈥撯€撯€撯€�
鈥撯€�
VQ100
鈥�
77
71
68
13
鈥�
TQ144
鈥�
91
100
鈥�
鈥撯€撯€撯€�
鈥撯€�
PQ208
鈥�
133
151
34
151
34
154
35
154
35
FG144
鈥�
96
97
24
972597259725
FG2565,6
鈥�
157
38
178
38
177
43
177
44
FG4846
鈥�
194
38
235
60
300
74
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User鈥檚 Guide
to ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
the ProASIC3 FPGA Fabric User鈥檚 Guide for position assignments of the 15 LVPECL pairs.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 or QN132 packages.
6. FG256 and FG484 are footprint-compatible packages.
Table 1 ProASIC3 FPGAs Package Sizes Dimensions
Package
CS121
QN48
QN68
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Length 脳 Width
(mm\mm)
6 脳 6
8 脳 8
14 脳 14
20 脳 20
28 脳 28
13 脳 13
17 脳 17
23 脳 23
Nominal Area
(mm2)
36
64
196
400
784
169
289
529
Pitch (mm)
0.5
0.4
0.5
1.0
Height (mm)
0.99
0.90
0.75
1.00
1.40
3.40
1.45
1.60
2.23
鐩搁棞PDF璩囨枡
PDF鎻忚堪
M1A3P250-1PQG208I IC FPGA 1KB FLASH 250K 208-PQFP
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鐩搁棞浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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A3P250-1PQG144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P250-1PQG144I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P250-1PQG144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P250-1PQG208 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 250K 208-PQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ProASIC3 妯欐簴鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:289-CSP锛�14x14锛�