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參數(shù)資料
| 型號(hào)： | A3P030-FQNG68 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 768 CLBS, 30000 GATES, 350 MHz, QCC68 |
| 封裝： | 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, GREEN, QFN-68 |
| 文件頁數(shù)： | 48/49頁 |
| 文件大?。?/td> | 5893K |
| 代理商： | A3P030-FQNG68 |
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ProASIC3 DC and Switching Characteristics
v1.3
2 - 81
Table 2-102 A3P250 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63
ns
tRCKH
Input HIGH Delay for Global Clock
0.781.04 0.891.181.041.391.251.66
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-103 A3P400 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75
ns
tRCKH
Input HIGH Delay for Global Clock
0.861.11 0.981.271.151.491.381.79
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
Mhz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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參數(shù)描述 |
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