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參數(shù)資料
| 型號： | A3423LLTR-T |
| 元件分類： | 磁阻傳感器 |
| 英文描述： | MAGNETIC FIELD SENSOR-HALL EFFECT, -5.5-5.5mT, 500mV, RECTANGULAR, SURFACE MOUNT |
| 封裝： | LEAD FREE, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 258K |
| 代理商： | A3423LLTR-T |
Dual Channel Hall Effect Direction Detection Sensor IC
A3423
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The integrated circuit contains an internal voltage regulator that
powers the Hall elements and both the analog and digital cir-
cuitry. This regulator allows operation over a wide supply voltage
range and provides some immunity to supply noise. The device
also contains logic circuitry that decodes the direction of rotation
of the ring magnet.
Quadrature/Direction Detection
Internal logic circuitry provides
outputs representing the speed and direction of the magnetic
field across the face of the package. For the direction signal to be
appropriately updated, a quadrature relationship must be main-
tained between the target magnetic pole width, the pitch between
the two Hall elements (E1 and E2) in the device, and, to a lesser
extent, the magnetic switchpoints.
For optimal design, the device should be actuated by a ring
magnet that presents to the front of the device a field with a pole
width two times the Hall element-to-element spacing. This will
produce a sinusoidal magnetic field whose period (denoted as Τ)
is then four times the element-to-element spacing. A quadrature
relationship can also be maintained for a ring magnet with fields
having a period that satisfies the relationship:
nΤ/4 = 1.63 mm ,
where n is any odd integer. Therefore, ring magnets with pole-
pair spacing equal to 6.52 mm (n = 1), 2.17 mm (n = 3), 1.3 mm
(n = 5), and so forth, are permitted.
The response of the device to the magnetic field produced by a
rotating ring magnet is shown in the Performance Characteristics
section. Note the phase shift between the two integrated Hall ele-
ments.
Outputs
The device provides up to four saturated outputs: target
direction (DIR pin), E1 element output (OUTA pin), E2 element
output (OUTB pin), and target speed (SPD pin).
DIR provides the direction output of the device and is defined
as off (high) for targets moving in the direction from E1 to E2
and on (low) for the direction E2 to E1. SPD provides an XORed
output of the two Hall elements (see figure 1). Because of inter-
nal delays, DIR is always updated before SPD and is updated at
every transition of OUTA and OUTB (internal) allowing the use
of up-down counters without the loss of pulses.
Power-on State
At power on, the logic circuitry is reset to pro-
vide an off (high) state for all the outputs. If any of the channels
is subjected to a field greater than BOP, the internal logic will set
accordingly, and the outputs will switch to the expected state.
Power-on Time
This characteristic, tON, is the elapsed time from
when the supply voltage reaches the device supply minimum
until the device output becomes valid (see figure 2).
Functional Description
Figure 1
Figure 2
+B
0
–B
+B
0
–B
OUTA
OUTB
SPD
DIR
Target changes direction of rotation
t
d
(OUTA XOR
OUTB)
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