參數(shù)資料
型號: A3250JUATL
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PSSO3
封裝: ULTRA MINI, TO-92, SIP-3
文件頁數(shù): 2/15頁
文件大?。?/td> 730K
代理商: A3250JUATL
10
A3250-DS
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
Allegro MicroSystems, Inc.
Field-Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switches
A3250 and A3251
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bitfield address sequence.
3. When permanently setting the bitfield, a long VPH fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.) When
provisionally trying a value, a short VPH pulse.
4. When permanently setting the bitfield, the level of VCC must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bitfields, VCC must be maintained at VPL between pulse
sequences, in order to maintain the prior bitfield settings while
preparing to set additional bitfields.
Bitfields that are not set are evaluated as zeros. The bitfield-level
fuses for 0 value bitfields are never blown. This prevents inad-
vertently setting the bitfield to 1. Instead, blowing the device-
level fuse protects the 0 bitfields from being accidentally set in
the future.
Two pulse sequences for provisionally trying the calibration
value 5 are shown in figure 2. Because the bitfields must be set
individually, 510 must be programmed as binary 101. Bit 3 is
set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012,
which is 110). Bit 2 is ignored, and so remains 0.
Two pulse sequences for permanently setting the calibration
value 5 are shown in figure 3. The final VPH pulse, which was
used as a short delimiter when trying values, is maintained for a
longer period, enough to blow the corresponding bitfield-level
fuse.
VPH
V+
t
VPM
VPL
0
Encode 001002 (410)
Enable
7 pulses
Address
Blow
Enable
Encode 000012 (110)
Figure 3. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bitfield address 3 and bitfield address 1).
VPH
V+
t
VPM
VPL
0
Try 001002 (410)
Enable
7 pulses
Address
Clear
Enable
Try 000012 (110)
Optional
Monitoring
Optional
Monitoring
Figure 2. Pulse sequence to provisionally try calibration value 5 (101 binary, or bitfield
address 3 and bitfield address 1).
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