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  • 參數(shù)資料
    型號: A1425A-1PLG84C
    元件分類: FPGA
    英文描述: FPGA, 310 CLBS, 2500 GATES, 150 MHz, PQCC84
    封裝: PLASTIC, LCC-84
    文件頁數(shù): 9/68頁
    文件大?。?/td> 489K
    代理商: A1425A-1PLG84C
    1-191
    Accelerator Series FPGAs – ACT 3 Family
    Active Power Component
    Power dissipation in CMOS devices is usually dominated by
    the active (dynamic) power dissipation. This component is
    frequency dependent, a function of the logic and the external
    I/O. Active power dissipation results from charging internal
    chip capacitances of the interconnect, unprogrammed
    antifuses, module inputs, and module outputs, plus external
    capacitance due to PC board traces and load device inputs.
    An additional component of the active power dissipation is
    the totem-pole current in CMOS transistor pairs. The net
    effect can be associated with an equivalent capacitance that
    can be combined with frequency and voltage to represent
    active power dissipation.
    Equivalent Capacitance
    The power dissipated by a CMOS circuit can be expressed by
    the Equation 2.
    Power (uW) = CEQ * VCC
    2 * F
    (2)
    Where:
    CEQ is the equivalent capacitance expressed in pF.
    VCC is the power supply in volts.
    F is the switching frequency in MHz.
    Equivalent capacitance is calculated by measuring ICCactive
    at a specified frequency and voltage for each circuit
    component of interest. Measurements have been made over a
    range of frequencies at a fixed value of VCC. Equivalent
    capacitance is frequency independent so that the results may
    be used over a wide range of operating conditions. Equivalent
    capacitance values are shown below.
    CEQ Values for Actel FPGAs
    To calculate the active power dissipated from the complete
    design, the switching frequency of each part of the logic must
    be known. Equation 3 shows a piece-wise linear summation
    over all components.
    Power =VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs
    + (p * (CEQO+ CL) * fp)outputs
    + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
    + 0.5 * (q2 * CEQCR * fq2)routed_Clk2
    + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk
    + (s2 * CEQCI * fs2)IO_Clk]
    (3)
    Where:
    Modules (CEQM)
    6.7
    Input Buffers (CEQI)
    7.2
    Output Buffers (CEQO)
    10.4
    Routed Array Clock Buffer Loads (CEQCR)
    1.6
    Dedicated Clock Buffer Loads (CEQCD)
    0.7
    I/O Clock Buffer Loads (CEQCI)
    0.9
    m
    = Number of logic modules switching at fm
    n
    = Number of input buffers switching at fn
    p
    = Number of output buffers switching at fp
    q1
    = Number of clock loads on the first routed
    array clock
    q2
    = Number of clock loads on the second routed
    array clock
    r1
    = Fixed capacitance due to first routed array
    clock
    r2
    = Fixed capacitance due to second routed array
    clock
    s1
    = Fixed number of clock loads on the dedicated
    array clock
    s2
    = Fixed number of clock loads on the dedicated
    I/O clock
    CEQM
    = Equivalent capacitance of logic modules in pF
    CEQI
    = Equivalent capacitance of input buffers in pF
    CEQO
    = Equivalent capacitance of output buffers in
    pF
    CEQCR = Equivalent capacitance of routed array clock
    in pF
    CEQCD = Equivalent capacitance of dedicated array
    clock in pF
    CEQCI
    = Equivalent capacitance of dedicated I/O clock
    in pF
    CL
    = Output lead capacitance in pF
    fm
    = Average logic module switching rate in MHz
    fn
    = Average input buffer switching rate in MHz
    fp
    = Average output buffer switching rate in MHz
    fq1
    = Average first routed array clock rate in MHz
    fq2
    = Average second routed array clock rate in
    MHz
    fs1
    = Average dedicated array clock rate in MHz
    fs2
    = Average dedicated I/O clock rate in MHz
    相關(guān)PDF資料
    PDF描述
    A1425A-1PLG84I FPGA, 310 CLBS, 2500 GATES, PQCC84
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    A1425A-1PQ160C FPGA, 310 CLBS, 2500 GATES, 150 MHz, PQFP160
    A1425A-1PQ160I FPGA, 310 CLBS, 2500 GATES, PQFP160
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    A1425A-1PLG84I 功能描述:IC FPGA 2500 GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
    A1425A1PQ100C 制造商:Microsemi SOC Products Group 功能描述:Field-Programmable Gate Array, 310 Cell, 100 Pin, Plastic, QFP
    A1425A-1PQ100C 功能描述:IC FPGA 2500 GATES 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
    A1425A-1PQ100I 功能描述:IC FPGA 2500 GATES 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
    A1425A-1PQ160C 功能描述:IC FPGA 2500 GATES 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)