Table 2-20 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, T
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A1240A-1PG132C
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 19/54闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 4K GATES 132-CPGA COM
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 21
绯诲垪锛� ACT™ 2
LAB/CLB鏁�(sh霉)锛� 684
杓稿叆/杓稿嚭鏁�(sh霉)锛� 104
闁€鏁�(sh霉)锛� 4000
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 閫氬瓟
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 132-BCPGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 132-CPGA锛�34.54x34.54锛�
Detailed Specifications
2- 20
R e visio n 8
Table 2-20 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70掳C
TTL Output Module Timing1
鈥�2 Speed
鈥�1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tDLH
Data to Pad High
8.1
9.0
10.6
ns
tDHL
Data to Pad Low
10.2
11.4
13.4
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.3
11.5
13.5
ns
tDHL
Data to Pad Low
8.5
9.6
11.2
ns
tENZH
Enable Pad Z to High
9.0
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.8
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.3
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
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