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參數資料
| 型號： | 9P936AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 188K |
| 代理商： | 9P936AGLF |
IDTTM/ICSTM
Low Skew Dual Bank DDR I/II Fan-out Buffer
1084C 12/03/09
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
4
Recommended Operating Condition (VDDQ2.5/1.8 = 1.8V +/- 0.1V) (see note1)
TA = 0 - 70°C; Supply Voltage AVDD = 2.5V+/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low level input voltage
VIL
BUF_INT, BUF_INC
0.35 x VDDQ
V
High level input voltage
VIH
BUF_INT, BUF_INC
0.65 x VDDQ
V
DC input signal voltage
(note 2)
VIN
-0.3
VDDQ + 0.3
V
DC - BUF_INT, BUF_INC
0.3
VDDQ + 0.4
V
AC - BUF_INT, BUF_INC
0.6
VDDQ + 0.4
V
Output differential cross-
voltage (note 4)
VOX
VDDQ/2 - 0.1
VDDQ/2 + 0.1
V
Input differential cross-
voltage (note 4)
VIX
VDDQ/2 - 0.15
VDDQ/2
VDDQ/2 + 0.15
V
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allow able DC excursion of differential input.
4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at w hich the differential signal must be changed.
Differential input signal
voltage (note 3)
VID
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for sw itching, w here VTR is the true input level and
VCP is the complimentary input level.
SPECIFICATION
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