參數(shù)資料
型號： 9LRS4103YKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC32
封裝： ROHS COMPLIANT, PLASTIC, MLF-32
文件頁數(shù)： 1/15頁
文件大小： 158K
代理商： 9LRS4103YKLFT
ICS9LRS4103
IDT PC MAIN CLOCK
1520A—03/16/10
32-pin CK505 for Intel Systems
1
DATASHEET
Pin Configuration
Recommended Application:
CK505 clock, 32-pin for 5 series Intel chipsets
Output Features:
1 - CPU differential low power push-pull pairs
1 - SRC differential low power push-pull pairs
1 - Selectable 120MHz or 100MHz CK_SSC_Disp low power
push-pull pair
1 - SATA/SRC selectable differential low power push-pull pair
1 - DOT differential low power push-pull pair
1 - REF, 14.318MHz
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
+/- 100ppm frequency accuracy on all outputs
SRC are PCIe Gen2 compliant
Features/Benefits:
Supports spread spectrum modulation, default is 0.5%
down spread
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Does not require external pass transistor for voltage
regulator
Integrated 33 series resistors on differential outputs,
Zo=50
Not recommended for new designs. The last time buy
date for this product is 5/19/2011.
Please refer to PDN K-10-18.
Table 1: CPU Frequency Select Table
G
N
D
X
T
A
L
S
E
L
_
S
A
T
A
_
N
S
#
V
D
X
T
A
L
G
N
D
R
E
F
R
E
F
1
4
.3
1
8
M
/F
S
L
C
**
V
D
R
E
F
1
4
M
C
K
P
W
R
G
D
/P
D
#
_
3
.3
V
D
C
P
U
32 31 30 29 28 27 26 25
X1 1
24 CPUC0
X2 2
23 CPUT0
SMBCLK_3.3 3
22 GNDCPU
SMBDAT_3.3 4
21 SEL_120M#
VDD96 5
20 VDDSRC
DOT96T 6
19 SRC2C
DOT96C 7
18 SRC2T
GND96 8
17 GNDSRC
9
10 11 12 13 14 15 16
G
N
D
S
C
K
_
S
C
_
D
IS
P
_
T
C
K
_
S
C
_
D
IS
P
_
C
V
D
S
C
V
D
S
A
T
A
S
R
C
1
T
/S
A
T
A
_
N
S
_
T
S
R
C
1
C
/S
A
T
A
_
N
S
_
C
G
N
D
S
A
T
A
** Internal Pull-Down Resistor
9LRS4103
FSLC
B0b7
CPU
MHz
SRC
MHz
REF
MHz
DOT
MHz
0 (Default)
133.33
1
100.00
1. FS
LC is a low-threshold input.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
100.00
14.318 96.00
SEL_120M#
Pin# 21
Pin# 10/11
Pulled Low
120MHz
Pulled High
100MHz
SEL_SATA_NS#
Pin# 31
Pin# 14/15
0
100MHz_nonSS
1
100MHz_SS
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