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參數(shù)資料
| 型號： | 9LPRS535CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 216K |
| 代理商： | 9LPRS535CFLF |
9
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
1461A—07/28/09
PCI_STOP# Power Management
SMBus OE Bit
PCI_STOP#
Stoppable
Free running
Stoppable
Free running
1
Running
0
Low
Running
CK= High
CK# = Low
Running
Disable
X
CPU_STOP# Power Management
SMBus OE Bit
Stoppable
Free running
1
Running
0
CK= High
CK# = Low
Running
Disable
X
CR# Power Management
SMBus OE Bit
CR#
CR# controlled
Free running
1
Running
0
Disable
X
PD# Power Management
Device State
w/o Latched input
w/Latched input
Latches Open
Low
Power Down
25MHz
M1
25MHz
Virtual Power Cycle
to Latches Open
25MHz
CPU1
CK= Pull down,
CK# = Low
CK= Pull down,
CK# = Low
CK= Pull down,
CK# = Low
Running
CK= Pull down
CK# = Low
Enable
CK= Pull down, CK# = Low
CK= Pull down,
CK# = Low
Low
Hi-Z
Single-ended Clocks
(Except SE1)
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
Low
SE1
w/B11b5 = 0
Enable
CK= Pull down, CK# = Low
Low
CPU_STOP#
Enable
Single-ended Clocks
Differential Clocks
(Except CPU)
Low
CK = Pull down, CK# = Low
CPU Clocks
Differential Clocks
(Except CPU)
SE1
w/B11b5 = 1
Differential Clocks
(Except CPU1)
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