參數(shù)資料
型號(hào)： 9LPRS501YKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 265K
代理商： 9LPRS501YKLFT
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1121F—02/23/09
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
15
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
SMBus Voltage
V
DD
2.7
5.5
V
1
Low-level Output Voltage
V
OLSMB
@ I
PULLUP
0.4
V
1
Current sinking at
V
OLSMB = 0.4 V
I
PULLUP
SMB Data Pin
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Maximum SMBus Operating
Frequency
F
SMBUS
Block Mode
100
kHz
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
7 Operation under these conditions is neither implied, nor guaranteed.
9 See PCI Clock-to-Clock Delay Figure
8 Maximum input voltage is not to exceed maximum VDD
Electrical Characteristics - SE1/2=25MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1,2
Clock period
T
period
25.00MHz output nominal
39.99600
40.00400
ns
1
Absolute min/max period
T
abs
25.00MHz output nominal
39.32360
40.67640
ns
1
Output High Voltage
V
OH
I
OH = -1 mA
2.4
V
1
Output Low Voltage
V
OL
I
OL = 1 mA
0.4
V
1
V
OH @MIN = 1.0 V
-29
mA
1
V
OH@MAX = 3.135 V
-23
mA
1
V
OL @ MIN = 1.95 V
29
mA
1
V
OL @ MAX = 0.4 V
27
mA
1
Rising Edge Slew Rate
t
SLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
t
FLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
Duty Cycle
d
t1
V
T = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T = 1.5 V
500
ps
1
Jitter, Long Term
t
LTJ
V
T = 1.5 V @ 10us delay
3000
ps
1
Output High Current
I
OH
Output Low Current
I
OL
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