參數(shù)資料
型號(hào)： 9LPRS501SKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁(yè)數(shù)： 27/27頁(yè)
文件大?。?/td> 228K
代理商： 9LPRS501SKLFT
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
9
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
33
VDDSRC_IO
PWR Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
34
SRCT4
I/O
True clock of differential SRC clock pair 4
35
SRCC4
I/O
Complement clock of differential SRC clock pair 4
36
GNDSRC
PWR Ground pin for SRC clocks.
37
SRCT9
OUT
True clock of differential SRC clock pair.
38
SRCC9
OUT
Complement clock of differential SRC clock pair.
39
SRCC11/CR#_G
I/O
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled
in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can
then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
40
SRCT11/CR#_H
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled
in byte 3, bit 6 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can
then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration
space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
41
SRCT10
OUT
True clock of differential SRC clock pair.
42
SRCC10
OUT
Cpmplement clock of differential SRC clock pair.
43
VDDSRC_IO
PWR Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance
44
CPU_STOP#/SRCC5
I/O
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin
6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
45
PCI_STOP#/SRCT5
I/O
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin
6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
46
VDDSRC
PWR VDD pin for SRC internal circuits, 3.3V nominal
47
SRCC6
OUT
Complement clock of low power differential SRC clock pair.
48
SRCT6
OUT
True clock of low power differential SRC clock pair.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPRS501YGLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
9LPRS501YKLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
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