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參數(shù)資料
| 型號： | 9LPRS365BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封裝： | PLASTIC, VQFN-64 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 9LPRS365BKLFT |
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24
ICS9LPRS365
Datasheet
1218—09/01/10
Byte 17 VCO Frequency Control Register PLL3
Bit
Pin
Name
Description
Type
0
1
Default
7
N Div8
N Divider 8
RW
-
X
6
N Div9
N Divider 9
RW
-
X
5
M Div5
RW
-
X
4
M Div4
-
X
3
M Div3
RW
-
X
2
M Div2
RW
-
X
1
M Div1
RW
-
X
0
M Div0
RW
-
X
Byte 18 VCO Frequency Control Register PLL3
Bit
Pin
Name
Description
Type
0
1
Default
7
N Div7
RW
-
X
6
N Div6
RW
-
X
5
N Div5
RW
-
X
4
N Div4
RW
-
X
3
N Div3
RW
-
X
2
N Div2
RW
-
X
1
N Div1
RW
-
X
0
N Div0
RW
-
X
Byte 19 Spread Spectrum Control Register PLL3
Bit
Pin
Name
Description
Type
0
1
Default
7
SSP7
RW
-
X
6
SSP6
RW
-
X
5
SSP5
RW
-
X
4
SSP4
RW
-
X
3
SSP3
RW
-
X
2
SSP2
RW
-
X
1
SSP1
RW
-
X
0
SSP0
RW
-
X
Byte 20 Spread Spectrum Control Register PLL3
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
0
6
SSP14
RW
-
x
5
SSP13
RW
-
X
4
SSP12
RW
-
X
3
SSP11
RW
-
X
2
SSP10
RW
-
X
1
SSP9
RW
-
X
0
SSP8
RW
-
X
Byte 21 M/N Enables
Bit
Pin
Name
Description
RW
0
1
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
Reserved
RW
0
2
Reserved
RW
0
1
M/N Enable
CPU PLL M/N Enable
RW
Disable
Enable
0
M/N Enable
SRC/PCI PLL M/N Enable
RW
Disable
Enable
0
The decimal representation of M Div (5:0) is equal
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
*These bits are disabled if TME is latched to 1
The decimal representation of N Div (9:0) is equal to
VCO divider value. Default at power up = latch-in or
Byte 0 Rom table.
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
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