參數(shù)資料
型號(hào): 9LPRS365BGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù): 14/28頁
文件大?。?/td> 301K
代理商: 9LPRS365BGLFT
21
ICS9LPRS365
Datasheet
1218—09/01/10
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SRC3_OE
Output enable for SRC3
RW
Output Disabled
Output Enabled
1
6
SATA/SRC2_OE
Output enable for SATA/SRC2
RW
Output Disabled
Output Enabled
1
5
SRC1_OE
Output enable for SRC1
RW
Output Disabled
Output Enabled
1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
RW
Output Disabled
Output Enabled
1
3
CPU1_OE
Output enable for CPU1
RW
Output Disabled
Output Enabled
1
2
CPU0_OE
Output enable for CPU0
RW
Output Disabled
Output Enabled
1
PLL1_SSC_ON
Enable PLL1's spread modulation
RW
Spread Disabled
Spread Enabled
1
0
PLL3_SSC_ON
Enable PLL3's spread modulation
RW
Spread Disabled
Spread Enabled
1
Byte 5 Clock Request Enable/Configuration Register
Bit
Pin
Name
Description
Type
0
1
Default
7
CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 0 for this bit to take effect
RW
Disable CR#_A
Enable CR#_A
0
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
RW
CR#_A -> SRC0
CR#_A -> SRC2
0
5
CR#_B_EN
Enable CR#_B (clk req)
RW
Disable CR#_B
Enable CR#_B
0
4
CR#_B_SEL
Sets CR#_B -> SRC1 or SRC4
RW
CR#_B -> SRC1
CR#_B -> SRC4
0
3
CR#_C_EN
Enable CR#_C (clk req)
RW
Disable CR#_C
Enable CR#_C
0
2
CR#_C_SEL
Sets CR#_C -> SRC0 or SRC2
RW
CR#_C -> SRC0
CR#_C -> SRC2
0
1
CR#_D_EN
Enable CR#_D (clk req)
RW
Disable CR#_D
Enable CR#_D
0
CR#_D_SEL
Sets CR#_D -> SRC1 or SRC4
RW
CR#_D -> SRC1
CR#_D -> SRC4
0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
CR#_E_EN
Enable CR#_E (clk req) -> SRC6
RW
Disable CR#_E
Enable CR#_E
0
6
CR#_F_EN
Enable CR#_F (clk req) -> SRC8
RW
Disable CR#_F
Enable CR#_F
0
5
CR#_G_EN
Enable CR#_G (clk req) -> SRC9
RW
Disable CR#_G
Enable CR#_G
0
4
CR#_H_EN
Enable CR#_H (clk req) -> SRC10
RW
Disable CR#_H
Enable CR#_H
0
3
Reserved
RW
0
2
Reserved
RW
0
1
SSCD_STP_CRTL
If set, LCD_SS stops with PCI_STOP#
RW
Free Running
Stops with
PCI_STOP#
assertion
0
SRC_STP_CRTL
If set, SRCs
stop with PCI_STOP#
RW
Free Running
Stops with
PCI_STOP#
assertion
0
Byte 7 Vendor ID/ Revision ID
Bit
Pin
Name
Description
Type
0
1
Default
7
Rev Code Bit 3
R
0
6
Rev Code Bit 2
R
0
5
Rev Code Bit 1
R
1
4
Rev Code Bit 0
R
0
3
Vendor ID bit 3
R
0
2
Vendor ID bit 2
R
0
1
Vendor ID bit 1
R
0
Vendor ID bit 0
R
1
Revision ID
Vendor ID
ICS is 0001, binary
Vendor specific
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