參數(shù)資料
型號(hào): 9FG1901YK-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: PLASTIC, MO-220, MLF-72
文件頁數(shù): 6/17頁
文件大?。?/td> 233K
代理商: 9FG1901YK-T
14
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1:1 PLL N Div8
N Divider Prog bit 8
RW
X
Bit 6
1:1 PLL N Div9
N Divider Prog bit 9
RW
X
Bit 5
1:1 PLL M Div5
RW
X
Bit 4
1:1 PLL M Div4
RW
X
Bit 3
1:1 PLL M Div3
RW
X
Bit 2
1:1 PLL M Div2
RW
X
Bit 1
1:1 PLL M Div1
RW
X
Bit 0
1:1 PLL M Div0
RW
X
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1:1 PLL N Div7
RW
X
Bit 6
1:1 PLL N Div6
RW
X
Bit 5
1:1 PLL N Div5
RW
X
Bit 4
1:1 PLL N Div4
RW
X
Bit 3
1:1 PLL N Div3
RW
X
Bit 2
1:1 PLL N Div2
RW
X
Bit 1
1:1 PLL N Div1
RW
X
Bit 0
1:1 PLL N Div0
RW
X
SMBusTable: 1:1 PLL Output Divider Register (Rev H and higher)
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1:1 PLL OutDiv 3
PLL 2 Output Divider
RW
X
Bit 2
1:1 PLL OutDiv 2
PLL 2 Output Divider
RW
X
Bit 1
1:1 PLL OutDiv 1
PLL 2 Output Divider
RW
X
Bit 0
1:1 PLL OutDiv 0
PLL 2 Output Divider
RW
X
-
Byte 16
-
Byte 17
-
Byte 19
-
Byte 18
-
RESERVED
See Output Divider Table
N Divider Programming b(7:0)
RESERVED
M Divider Programming bits
相關(guān)PDF資料
PDF描述
9FG430AGILFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AFILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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