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參數(shù)資料
| 型號： | 9FG1200YF-1LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.635 MM PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 286K |
| 代理商： | 9FG1200YF-1LF-T |
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
3
Pin Description
PIN # PIN NAME
PIN TYPE
DESCRIPTION
1HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
2
CLK_IN
IN
Input for reference clock.
3
CLK_IN#
IN
"Complementary" reference clock input.
4
SMB_A0
IN
SMBus address bit 0 (LSB)
5OE0#
IN
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
6
DIF_0
OUT
0.7V differential true clock output
7
DIF_0#
OUT
0.7V differential complement clock output
8OE1#
IN
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
9
DIF_1
OUT
0.7V differential true clock output
10
DIF_1#
OUT
0.7V differential complement clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
GND
PWR
Ground pin.
13
DIF_2
OUT
0.7V differential true clock output
14
DIF_2#
OUT
0.7V differential complement clock output
15
OE2#
IN
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_3
OUT
0.7V differential true clock output
17
DIF_3#
OUT
0.7V differential complement clock output
18
OE3#
IN
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
19
DIF_4
OUT
0.7V differential true clock output
20
DIF_4#
OUT
0.7V differential complement clock output
21
OE4#
IN
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
22
VDD
PWR
Power supply, nominal 3.3V
23
GND
PWR
Ground pin.
24
DIF_5
OUT
0.7V differential true clock output
25
DIF_5#
OUT
0.7V differential complement clock output
26
OE5#
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
27
SMB_A1
IN
SMBus address bit 1
28
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
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相關代理商/技術參數(shù) |
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| 9FG1201CGLF | 制造商:INT_CIR_SYS 功能描述: |
| 9FG1201CGLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1,000 |
| 9FG1201HFLF | 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1201HFLFT | 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1201HGLF | 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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