- 您現(xiàn)在的位置：買賣IC網 > PDF目錄25565 > 9EPRS525AGILF (INTEGRATED DEVICE TECHNOLOGY INC) SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 PDF資料下載
參數(shù)資料
| 型號： | 9EPRS525AGILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 210K |
| 代理商： | 9EPRS525AGILF |
IDTTM
56-pin CK505 for Embedded Intel Systems
1614B—01/21/10
ICS9EPRS525
6
56-pin CK505 for Embedded Systems
1Signal is required to be monotonic in this region.
2 input leakage current does not include inputs with pull-up or pull-down resistors
4 Intentionally blank
7 Operation under these conditions is neither implied, nor guaranteed.
8 Frequency Select pins which have tri-level input
9 PCI3/CFG0 is optional
10 If present. Not all parts have this feature.
5 Maximum VIH is not to exceed VDD
6 Human Body Model
3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
250
ps
1
1Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS NOTES
Rising Edge Slew Rate
tSLR
Averaging on
2.5
4
V/ns
2, 3
Falling Edge Slew Rate
tFLR
Averaging on
2.5
4
V/ns
2, 3
Slew Rate Variation
tSLVAR
Averaging on
20
%
1, 10
Differential Voltage Swing
VSWING
Averaging off
300
mV
2
Crossing Point Voltage
VXABS
Averaging off
300
550
mV
1,4,5
Crossing Point Variation
VXABSVAR
Averaging off
140
mV
1,4,9
Maximum Output Voltage
VHIGH
Averaging off
1150
mV
1,7
Minimum Output Voltage
VLOW
Averaging off
-300
mV
1,8
Duty Cycle
DCYC
Averaging on
45
55
%
2
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
3000
ps
1,6
1Measurement taken for single ended waveform on a component test board (not in system)
2 Measurement taken from differential waveform on a component test board. (not in system)
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
6 Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.
7 The max voltage including overshoot.
8 The min voltage including undershoot.
10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
5 Only applies to the differential rising edge (Clock rising, Clock# falling)
相關PDF資料 |
PDF描述 |
|---|---|
| 9ERS3165BGILFT | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 9EX21501AKLFT | 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 9EX21501AKLF | 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 9EX21501AKILF | 21501 SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC64 |
| 9EX21801AKLF | PLL BASED CLOCK DRIVER, PQCC72 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9EPRS525AGILFT | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS525AGLF | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS525AGLFT | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9ERS3125BKILF | 功能描述:實時時鐘 EMBEDDED CK505 COMPATIBLE CLOCK RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| 9ERS3125BKILFT | 功能描述:時鐘合成器/抖動清除器 EMBEDDED CK505 COMPATIBLE CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。