參數(shù)資料
型號(hào): 9EPRS488CKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù): 10/22頁(yè)
文件大?。?/td> 266K
代理商: 9EPRS488CKLF
18
Integrated
Circuit
Systems, Inc.
ICS9EPRS488
Datasheet
1616—08/20/09
SMBus Table: CPU PLL Frequency Control Register
Byte
12
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte
13
Name
Control Function
Type
0
1
Default
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte
14
Name
Control Function
Type
0
1
Default
Bit 7
X
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
SMBUS Table: CPU Output Divider Register
Byte
15
Name
Control Function
Type
0
1
Default
Bit 7
CPU NDiv0
LSB N Divider Programming
RW
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
CPUDiv3
RW
0000:/2 ; 0100:/4
1000:/8 ; 1100:/16
X
Bit 2
CPUDiv2
RW
0001:/3 ; 0101:/6
1001:/12 ; 1101:/24
X
Bit 1
CPUDiv1
RW
0010:/5 ; 0110:/10
1010:/20 ; 1110:/40
X
Bit 0
CPUDiv0
RW
0011:/15 ; 0111:/18
1011:/36 ; 1111:/72
X
SMBUS Table: SB_SRC Frequency Control Register
Byte
16
Name
Control Function
Type
0
1
Default
Bit 7
N Div2
N Divider Prog bit 2
RW
X
Bit 6
N Div1
N Divider Prog bit 1
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
M Divider Programming
bit (5:0)
The decimal representation of M and N Divider in
Byte 16 and 17 configure the SB_SRC VCO
frequency. See M/N Caculation Tables for VCO
frequency formulas.
Spread Spectrum
Programming b(14:8)
Bytes 13 and 14 set the CPU/HTT/SRC/ATIG
spread pecentage.Please contact ICS for the
appropriate values.
CPU Divider Ratio
Programming Bits
Spread Spectrum
Programming b(7:0)
Bytes 13 and 14 set the CPU/HTT/SRC/ATIG
spread pecentage.Please contact ICS for the
appropriate values.
Reserved
N Divider Programming
b(10:3)
The decimal representation of M and N Divider in
Byte 11 and 12 will configure the VCO frequency.
Default at power up = Byte 3 Rom table. VCO
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) .
CPU M/N programming.
Reserved
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