- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25565 > 9DB833AFLF (INTEGRATED DEVICE TECHNOLOGY INC) 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 PDF資料下載
參數(shù)資料
| 型號： | 9DB833AFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | ROHS COMPLIANT, SSOP-48 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 226K |
| 代理商： | 9DB833AFLF |
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
4
9DB833
REV C 052411
Pin Descriptions (cont.)
PIN #
PIN NAME
PIN TYPE
DESCR IPTION
25
GND
PWR
Ground pin.
26
GND
PWR
Ground pin.
27
VDD
PWR
Power supply, nominal 3.3V
28
SMB_ADR_tri
IN
SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus
Addresses.
29
DIF_4#
OUT
0.7V differential Complementary clock output
30
DIF_4
OUT
0.7V differential true clock output
31
VDD
PWR
Power supply, nominal 3.3V
32
GND
PWR
Ground pin.
33
DIF_5#
OUT
0.7V differential Complementary clock output
34
DIF_5
OUT
0.7V differential true clock output
35
OE5#
IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
36
OE6#
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
37
DIF_6#
OUT
0.7V differential Complementary clock output
38
DIF_6
OUT
0.7V differential true clock output
39
VDD
PWR
Power supply, nominal 3.3V
40
PD#
IN
Asynchronous active low input pin used to power dow n the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
41
DIF_7#
OUT
0.7V differential Complementary clock output
42
DIF_7
OUT
0.7V differential true clock output
43
OE4#
IN
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
44
OE7#
IN
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
45
LOCK
OUT
3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved.
46
IREF
OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB833AFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DBL411AGLFT | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411AKLFT | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411AGLF | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BKILF | LOW SKEW CLOCK DRIVER, PQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB833AFLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGILF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGILFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB833AGLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。