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參數(shù)資料
| 型號： | 97ULP877AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-205, MO-225, FBGA-52 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 176K |
| 代理商： | 97ULP877AHLF-T |
Integrated
Circuit
Systems, Inc.
ICS97ULP877A
7116—03/27/07
Block Diagram
1.8V Low-Power Wide-Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Switching Characteristics:
Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667)
Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667)
OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667)
CYCLE - CYCLE jitter 40ps
52-Ball BGA
Top View
12345
6
A
CLKT1
CLKT0
CLKC0
CLKC5
CLKT5
CLKT6
B
CLKC1
GND
CLKC6
C
CLKC2
GND
NB
GND
CLKC7
D
CLKT2
VDDQ
OS
CLKT7
E
CLK_INT
VDDQ
NB
VDDQ
FB_INT
F
CLK_INC
VDDQ
NB
OE
FB_INC
G
AGND
VDDQ
FB_OUTC
H
AVDD
GND
NB
GND
FB_OUTT
J
CLKT3
GND
CLKT8
K
CLKC3
CLKC4
CLKT4
CLKT9
CLKC9
CLKC8
A
B
C
D
E
F
G
H
J
K
6
5
4
3
2
1
CLKT2
CLK_INT
GND
CLKC2
CLK_INC
VDDQ
AVDD
AGND
VDDQ
2
3
4
5
6
7
8
9
10
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
C
L
K
C
4
C
L
K
T
4
V
D
Q
C
L
K
C
3
V
D
Q
C
L
K
T
8
C
L
K
C
8
C
L
K
C
9
C
L
K
T
9
C
L
K
T
3
8
3
7
3
6
3
5
3
4
3
2
3
1
4
0
3
9
C
L
K
T
0
C
L
K
C
0
V
D
Q
C
L
K
T
1
V
D
Q
C
L
K
C
6
C
L
K
T
6
C
L
K
T
5
C
L
K
C
5
C
L
K
C
1
22
23
24
30
29
28
27
26
25
21
VDDQ
FB_INT
OS
CLKT7
FB_INC
OE
VDDQ
FB_OUTT
FB_OUTC
CLKC7
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
Powerdown
Control and
Test Logic
LD
or OE
(1)
LD , OS, or OE
(1)
OS
OE
LD
(1)
AVDD
PLL Bypass
PLL
FB_INT
FB_INC
GND
CLK_INT
CLK_INC
NOTE:
1. The Logic Detect (LD) powers down the device when a logic LOW is
applied to both CLK_INT and CLK+INC.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 97ULP877BHLF | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 97ULP877BHLFT | 功能描述:時鐘驅動器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 97ULP877BKLF/W | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 95MHZ TO 410MHZ 40PIN VFQFPN - Tape and Reel |
| 97ULP878AH | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AH - Trays |
| 97ULP878AHLF | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLF - Trays |
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