參數(shù)資料
型號: 95V842AFILF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, LEAD FREE, MO-137, SSOP-16
文件頁數(shù): 6/9頁
文件大小: 75K
代理商: 95V842AFILF-T
6
ICS95V842
0830B—11/24/08
GND
ICS95V842
VDD
VDD/2
V(CLKC)
SCOPE
C=14pF
-VDD/2
VDD/2
Z=60
Z=60
Z=50
Z=50
R=10
R=10
R=50
R=60
R=60
R=50
V(TT)
C=14pF
NOTE: V(TT) = GND
tc(n)
tc(n+1)
tjit(cc) =tc(n) ±tc(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS95V842
Figure 3. Cycle-to-Cycle Jitter
相關(guān)PDF資料
PDF描述
95V842YFLF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842YFILF 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842AFLF 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842AFLF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
95V842AF-T 95V SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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