參數(shù)資料
型號: 953002DFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 23/35頁
文件大?。?/td> 280K
代理商: 953002DFLF
3
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
29
3V66_0
OUT
3.3V 66.66MHz clock output
30
GND3V66
PWR
Ground pin for the 3.3V 66MHz clocks
31
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
32
GNDPCIEX
PWR
Ground pin for the PCI-EX outputs
33
PCIEXC5/PCI_PCIEX_STO
P#*
OUT
Complement clock of differential PCI_Express pair. / Active low signal that
stops all PCI and PCIEX clocks besides the free running clocks
34
PCIEXT5/CPU_STOP#*
OUT
True clock of differential PCI_Express pair./Stops all CPUCLK besides the
free running clocks
35
PCIEXC4
OUT
Complement clock of differential PCI_Express pair.
36
PCIEXT4
OUT
True clock of differential PCI_Express pair.
37
PCIEXC3
OUT
Complement clock of differential PCI_Express pair.
38
PCIEXT3
OUT
True clock of differential PCI_Express pair.
39
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
40
GNDPCIEX
PWR
Ground pin for the PCI-EX outputs
41
PCIEXC2
OUT
Complement clock of differential PCI_Express pair.
42
PCIEXT2
OUT
True clock of differential PCI_Express pair.
43
PCIEXC1
OUT
Complement clock of differential PCI_Express pair.
44
PCIEXT1
OUT
True clock of differential PCI_Express pair.
45
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
46
CPUCLKC2_ITP/PCIEXC0
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias./
Complement clock of differential PCIEX pair
47
CPUCLKT2_ITP/PCIEXT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
48
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
49
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
50
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
51
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
52
GNDCPU
PWR
Ground pin for the CPU outputs
53
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
54
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
55
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
56
GND
PWR
Ground pin.
相關(guān)PDF資料
PDF描述
953002CFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
953220640112 TELECOM, CORDLESS, BASEBAND CIRCUIT, PDSO16
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
953002DFLFT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
953004-1 制造商:TE Connectivity 功能描述:SOCKET HEADER 32WAY 制造商:TE Connectivity 功能描述:SOCKET, HEADER, 32WAY 制造商:TE Connectivity 功能描述:SOCKET, HEADER, 32WAY; Connector Type:Wire to Board; Contact Termination:Through Hole Right Angle; Gender:Receptacle; No. of Contacts:32; No. of Rows:2; Pitch Spacing:2.54mm; Contact Plating:Tin; Contact Material:Bronz ;RoHS Compliant: Yes
953-004-1-100-2 制造商:3M Electronic Products Division 功能描述:
953008BFLF 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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