參數(shù)資料
型號(hào): 951601AFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 66.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, GREEN, MO-118, SSOP-48
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 168K
代理商: 951601AFLF
5
ICS951601
Preliminary Prouct Preview
0663C—10/04/05
Byte 1: PCI1A Stop Clocks Register
(1 = enable, 0 = disable)
Byte 2: PCI2A Stop Clocks
Register (1 = enable, 0 = disable)
Byte 3: PCI2B Stop Clocks Register
(1 = enable, 0 = disable)
Byte 4: Reserved Register
(1 = enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
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r
c
s
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D
7
t
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B4
21
7
_
A
1
I
C
P
6
t
i
B3
21
6
_
A
1
I
C
P
5
t
i
B0
21
5
_
A
1
I
C
P
4
t
i
B9
11
4
_
A
1
I
C
P
3
t
i
B6
11
3
_
A
1
I
C
P
2
t
i
B5
11
2
_
A
1
I
C
P
1
t
i
B2
11
1
_
A
1
I
C
P
0
t
i
B1
11
0
_
A
1
I
C
P
t
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B#
n
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PD
W
Pn
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D
7
t
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B
5
3
12
_
A
2
I
C
P
6
t
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B
4
3
11
_
A
2
I
C
P
5
t
i
B
1
3
10
_
A
2
I
C
P
4
t
i
B
9
2
12
_
B
1
I
C
P
3
t
i
B
8
2
11
_
B
1
I
C
P
2
t
i
B
5
2
10
_
B
1
I
C
P
1
t
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B
-
Xd
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R
0
t
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B
-
Xd
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t
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B#
n
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PD
W
Pn
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p
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c
s
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D
7
t
i
B1
41
2
_
B
2
I
C
P
6
t
i
B0
41
1
_
B
2
I
C
P
5
t
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B7
31
0
_
B
2
I
C
P
4
t
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B-
X
d
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v
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R
3
t
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B-
X
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2
t
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B-
X
d
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R
1
t
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B-
X
d
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v
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R
0
t
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B-
X
d
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s
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R
t
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B#
n
i
PD
W
Pn
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p
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r
c
s
e
D
7
t
i
B8
41
z
H
M
8
4
6
t
i
B1
1
0
F
E
R
5
t
i
B-
X
d
e
v
r
e
s
e
R
4
t
i
B-
X
d
e
v
r
e
s
e
R
3
t
i
B-
X
d
e
v
r
e
s
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R
2
t
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B-
X
d
e
v
r
e
s
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R
1
t
i
B-
X
d
e
v
r
e
s
e
R
0
t
i
B-
X
d
e
v
r
e
s
e
R
Byte 5: Latched Input Read Back Register
(1= enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
X
B
2
L
E
S
6
t
i
B-
X
B
1
L
E
S
5
t
i
B-
X
A
2
L
E
S
4
t
i
B-
X
A
1
L
E
S
3
t
i
B-
X
d
e
v
r
e
s
e
R
2
t
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B-
X
d
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v
r
e
s
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R
1
t
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B-
X
d
e
v
r
e
s
e
R
0
t
i
B-
X
d
e
v
r
e
s
e
R
Byte 6: Reserved for Byte Count Register
(1= enable, 0 = disable)
t
i
B#
n
i
PD
W
Pn
o
i
t
p
i
r
c
s
e
D
7
t
i
B-
0
d
a
e
r
o
f
d
e
v
r
e
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R
t
n
u
o
c
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t
y
b
6
t
i
B-
0
d
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v
r
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s
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R
5
t
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B-
0
d
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v
r
e
s
e
R
4
t
i
B-
0
d
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r
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R
3
t
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B-
0
d
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R
2
t
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B-
1
d
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R
1
t
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B-
1
d
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s
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R
0
t
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B-
0
d
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v
r
e
s
e
R
Note: PWD = Power-Up Default
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