參數(shù)資料
型號(hào): 951462YGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù): 16/23頁
文件大?。?/td> 241K
代理商: 951462YGLFT
23
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
Revision History
Rev.
Issue Date Description
Page #
0.0
4/7/2005
Initial Release
-
0.1
4/15/2005 Added Timing Diagram
19
0.2
6/6/2005
1. SMBus Byte 5 bits[6:5] are changed from CPU_STOP Enable to RESERVED.
2. Updated LF Ordering Information from "Annealed Lead Free" to "RoHS Compliant".
11, 22
0.3
6/8/2005
Updated Timing Diagram.
19
0.4
9/9/2005
1. Updated all description: Changed RS680 to RS580.
2. Updated Pin Description: Pin 11 and 57.
3. Updated Block Diagram: Took out CPU_STOP#.
4. Updated Electrical Characteristics:
i. Input/Supply/Common Output Parameters: Took out
Operating Supply Current.
ii. USB: Updated Rise and Fall Time.
iii. REF: Updated Rise and Fall Time.
5. Updated LF Ordering Information.
1,
2,3,
4,
15,18,
22
0.5
9/22/2005 1. Updated Output Features.
1
0.6
2/8/2006
Updated pin description pin 30/31 and 42/43
2-3
A
3/22/2006
1. Updated REF and USB cycle to cycle jitter specs to tentative SB600 requirements.
2. Updated CPU skew and jitter numbers
3. Updated SRC and ATIG skew and jitter numbers
4. Move Data sheet to Preliminary
17, 18
B
5/26/2006 1. Updated REF and USB rise/fall time specs to tentative SB600 requirements.
18
C
7/25/2006 Updated Reference to CLKREQB# on Byte 4 to CLKREQA#.
11
D
9/15/2006 Updated Recommended Application.
1, 4
E
12/5/2006
1. Updated Table 3 description.
2. Updated SMBus Pin# association.
7,
10-11
F
12/12/2006 1. Updated REF duty cycle to 56/44%.
18
G
1/30/2007 1. Updated REF Rise/Fall time spec
18
H
3/5/2007
1. Updated pinout and pin description for pin #61
1, 3
I
5/23/2007 Added Max Junction Temperature.
15
J
3/16/2009 Changed Cycle-to-cycle Jitter spec from 85 to 125ps.
17
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