參數(shù)資料
型號(hào)： 93C66AEST
廠商： Microchip Technology Inc.
英文描述： Standard Recovery Rectifier; Current Rating:125A; Forward Current:125A; Forward Voltage:2.5V; Leaded Process Compatible:Yes; Mounting Type:Through Hole; Package/Case:DO-8; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述： 4K的微絲兼容串行EEPROM
文件頁(yè)數(shù)： 5/24頁(yè)
文件大小： 405K
代理商： 93C66AEST
2003 Microchip Technology Inc.
DS21795B-page 5
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.0
FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to V
CC
, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the Read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
Data Protection
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an
EWEN
instruction must be
performed before the initial
ERASE
or
WRITE
instruction
can be executed.
Block Diagram
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
V
CC
V
SS
*ORG input is not available on A/B devices
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
93C66AESTG 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM
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93C66A-I/MCG 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM
93C66A-I/MS 功能描述:電可擦除可編程只讀存儲(chǔ)器 512x8 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
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