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參數(shù)資料
| 型號(hào)： | 935272023125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, INVERTED OUTPUT, PDSO5 |
| 封裝： | SOT-753, 5 PIN |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大小： | 70K |
| 代理商： | 935272023125 |
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2001 Apr 04
11
Philips Semiconductors
Product specication
Single D-type ip-op; positive-edge trigger
74LVC1G80
handbook, full pagewidth
VEXT
VCC
VI
VO
MNA616
D.U.T.
CL
RT
RL
PULSE
GENERATOR
Fig.7 Load circuitry for switching times.
VCC
VI
CL
RL
VEXT
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
1.65 to 1.95 V
VCC
30 pF
1 k
open
GND
2
× VCC
2.3 to 2.7 V
VCC
30 pF
500
open
GND
2
× VCC
2.7 V
50 pF
500
open
GND
6 V
3.0 to 3.6 V
2.7 V
50 pF
500
open
GND
6 V
4.5 to 5.5 V
VCC
50 pF
500
open
GND
2
× VCC
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
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