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參數資料
| 型號： | 935272018125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5 |
| 封裝： | PLASTIC, SC-74A, SOT-753, 5 PIN |
| 文件頁數： | 14/23頁 |
| 文件大小： | 145K |
| 代理商： | 935272018125 |
Philips Semiconductors - PIP - 74LVC1G125; Bus buffer/line driver; 3-state
Product Information
74LVC1G125; Bus
buffer/line driver; 3-
state
Information as of 2003-04-22
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Block diagram
topGeneral description
The 74LVC1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
The input can be driven from either 3.3 or 5 V devices. This feature allows the use of this device in a mixed 3.3 and 5 V
environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output,
preventing the damaging backflow current through the device when it is powered down.
The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by
the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state.
topFeatures
q
Wide supply voltage range from 1.65 to 5.5 V
q
High noise immunity
q
Complies with JEDEC standard:
r
JESD8-7 (1.65 to 1.95 V)
r
JESD8-5 (2.3 to 2.7 V)
r
JESD8B/JESD36 (2.7 to 3.6 V).
q
+-24 mA output drive (VCC = 3.0 V)
q
CMOS low power consumption
q
Latch-up performance exceeds 250 mA
q
Direct interface with TTL levels
q
Inputs accept voltages up to 5 V
q
Multiple package options
q
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
q
Specified from -40 to +125 Cel.
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVC1G125GW.html (1 of 3) [May-12-2003 2:58:49 PM]
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