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參數(shù)資料
| 型號(hào)： | 935269733112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-163-1, SO-20 |
| 文件頁(yè)數(shù)： | 19/20頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | 935269733112 |
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2002 Feb 26
8
Philips Semiconductors
Product specication
Octal D-type ip-op; positive edge-trigger;
3-state
74ALVC374
AC CHARACTERISTICS
Note
1. All typical values are measured at Tamb =25 °C.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
VCC (V)
40 to +85
MIN.
TYP.(1)
MAX.
tPHL/tPLH
propagation delay CP to Qn
see Figs 6 and 9
1.65 to 1.95
1.0
3.1
6.4
ns
2.3 to 2.7
1.0
2.3
3.9
ns
2.7
1.0
2.5
3.6
ns
3.0 to 3.6
1.0
2.5
3.6
ns
tPZH/tPZL
3-state output enable time
OE to Qn
see Figs 8 and 9
1.65 to 1.95
1.0
3.2
6.4
ns
2.3 to 2.7
1.0
2.6
4.5
ns
2.7
1.0
3.2
4.6
ns
3.0 to 3.6
1.0
2.4
4.0
ns
tPHZ/tPLZ
3-state output disable time
OE to Qn
see Figs 8 and 9
1.65 to 1.95
1.5
3.6
7.0
ns
2.3 to 2.7
1.0
2.3
4.4
ns
2.7
1.5
2.9
4.4
ns
3.0 to 3.6
1.0
2.8
4.4
ns
tW
clock pulse with HIGH or LOW
see Figs 7 and 9
1.65 to 1.95
3.8
1.1
ns
2.3 to 2.7
3.3
0.9
ns
2.7
3.3
0.8
ns
3.0 to 3.6
3.3
1.2
ns
tsu
set-up time Dn to CP
see Figs 7 and 9
1.65 to 1.95
0.8
0.1
ns
2.3 to 2.7
0.8
0.1
ns
2.7
0.8
0.3
ns
3.0 to 3.6
0.8
0.0
ns
th
hold time Dn to CP
see Figs 7 and 9
1.65 to 1.95
0.8
0.1
ns
2.3 to 2.7
0.8
0.1
ns
2.7
0.8
0.4
ns
3.0 to 3.6
0.7
0.1
ns
fmax
maximum clock pulse frequency see Figs 6 and 9
2.3 to 2.7
100
200
MHz
2.7
100
200
MHz
3.0 to 3.6
150
300
MHz
相關(guān)PDF資料 |
PDF描述 |
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| 935269733118 | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 935269734118 | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 935269734112 | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 935269735112 | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 935269735118 | ALVC/VCX/A SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
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