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參數(shù)資料
| 型號： | 935269556118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 86K |
| 代理商： | 935269556118 |
Philips Semiconductors
Product data
PCK2057
70 – 190 MHz I2C differential 1:10 clock driver
2001 Jun 12
5
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and “—”) should be designed as “Don’t Care”. It is expected that the controller will force all of these bits to a
“0” level.
All register bits labeled “Initialize to 0” must be written to zero during initialization. Failure to do so may result in a higher than normal operating
current.
Byte 0:
Active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
INITIAL VALUE
DESCRIPTION
7
2, 3
CLK0, CLK0
1
Enable/Disable Outputs
6
5, 6
CLK1, CLK1
1
Enable/Disable Outputs
5
9, 10
CLK2, CLK2
1
Enable/Disable Outputs
4
19, 20
CLK3, CLK3
1
Enable/Disable Outputs
3
22, 23
CLK4, CLK4
1
Enable/Disable Outputs
2
47, 46
CLK5, CLK5
1
Enable/Disable Outputs
1
44, 43
CLK6, CLK6
1
Enable/Disable Outputs
0
40, 39
CLK7, CLK7
1
Enable/Disable Outputs
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 1:
Active/inactive register
1 = enable; 0 = disable
BIT
PIN#
NAME
INITIAL VALUE
DESCRIPTION
7
30, 29
CLK8, CLK8
1
Enable/Disable Outputs
6
27, 26
CLK9, CLK9
1
Enable/Disable Outputs
5
—
0
Reserved
4
—
0
Reserved
3
—
0
Reserved
2
—
0
Reserved
1
—
0
Power-Down Mode Disable/Enable
0
—
0
HCSL Enable/Disable
NOTE:
1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
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