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參數(shù)資料
| 型號： | 935268252551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 49/80頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252551 |
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Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
50
Bit 16:
R/W
Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’
configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2
pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa.
Bit 11:
R/W
Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when
set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).
Bit 10:
R/W
Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).
Disables such interrupts when clear (0) (regardless of ITXINTE contents).
Bit 9:
R/W
Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1).
Disables such interrupts when clear (0) (regardless of IRXINTE contents).
Bit 8:
R/W
Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such
interrupts when clear (0) (regardless of LNKPHYINTE contents).
Bit 3:
R
Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source is in the Asynchronous Transmitter/
Receiver Interrupt Acknowledge/Source register.
Bit 2:
R
AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.
Bit 1:
R
AV Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.
Bit 0:
R
Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register.
13.1.8
Timer (TIMER) – Base Address: 0x01C
PRELOAD
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01096
31 30
TMGOST
OP
TMCONT
TMBRE
Reset Value
Bit 31:
R/W
TMGOSTOP: Timer Go/Stop, when = 1 start timer; when = 0 stop timer.
Bit 30:
R/W
TMCONT: Timer Continuous, when = 1 continuously operate timer; when = 0 operate timer for one timing cycle,
then stop.
Bit 29:
R/W
TMBRE: Timer Bus Reset Enable, when = 1, start the timer at the beginning of a bus reset; when = 0 start the timer
from the TMGOSTOP bit setting.
Bit 23..0:
R/W
Timer preload bits. Load a number into the timer preload bits with the most significant bit in the higher numbered bit
position; the least significant bit in the timer preload register is bit 0. The basic timing unit is 1/(2*CLK25) or 80.14
nanoseconds. The maximum timer time-out is about 1.34 seconds ((2^24)–1 units). The timer uses the preload
value inputted by the host into bits 0 through 23 of this register. The preload value is placed in the actual
timer/counter (invisible to outside world) and this value is decremented by 1 for each unit of time. The timer
eventually counts down to zero and then it sets the TIMER interrupt flag bit in register 0x008, LINKPHYINTACK
(assuming the interrupt was enabled by the ETIMER bit). Depending on the setting of the TMCONT bit in this
register, the timer preload value may be automatically reloaded into the timer/counter (when TMCONT = 1) with the
timing cycle automatically re-starting, or the timer will simply interrupt and stop (when TMCONT bit = 0). TMBRE
adds a mode to the timer operation which starts the timing automatically at the start of a 1394 bus reset. When
TMBRE is set (1), the TMGOSTOP bit function is disabled; the TMCONT bit function is still available.
NOTE: When TMCONT = 1, failing to acknowledge a TIMER interrupt has no effect on the starting/restarting of the
timer; if an interrupt is not acknowledged (bit reset), the timer will continue to time out and restart.
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