參數(shù)資料
型號(hào)： 935263293512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 24/48頁(yè)
文件大小： 324K
代理商： 935263293512
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
30
when the CPU reads the receive FIFO, only if (after this read) there
are no more characters in the FIFO – the Rx FIFO becomes empty.
SRB—Channel B Status Register
The bit definitions for this register are identical to the bit definitions
for SRA, except that all status applies to the Channel B receiver and
transmitter and the corresponding inputs and outputs.
OPCR—Output Port Configuration Register
OPCR OUTPUT PORT CONFIGURATION REGISTER
Addr
Bit 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OPCR
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
0x0D
0 = OPR[7]
0 = OPR[6]
0 = OPR[5]
0 = OPR[4]
00 = OPR[3]
00 = OPR[2]
1 = TxRDY B
1 = TxRDY A
1 = RxRDY/FFULL B
1 = RxRDY/FFULL A
01 = C/T OUTPUT
01 = TxCA(16X)
10 = TxCB(1X)
10 = TxCA(1X)
11 = RxCB(1X)
11 = RxCA(1X)
OPCR[7]—OP7 Output Select
This bit programs the OP7 output to provide one of the following:
0
The complement of OPR[7].
1
The Channel B transmitter interrupt output which is the
complement of ISR[4]. When in this mode OP7 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[6]—OP6 Output Select
This bit programs the OP6 output to provide one of the following:
0
The complement of OPR[6].
1
The Channel A transmitter interrupt output which is the
complement of ISR[0]. When in this mode OP6 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[5]—OP5 Output Select
This bit programs the OP5 output to provide one of the following:
0
The complement of OPR[5].
1
The Channel B receiver interrupt output which is the
complement of ISR[5]. When in this mode OP5 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[4]—OP4 Output Select
This field programs the OP4 output to provide one of the following:
0
The complement of OPR[4].
1
The Channel A receiver interrupt output which is the
complement of ISR[1]. When in this mode OP4 acts as an
open-drain output. Note that this output is not masked by the
contents of the IMR.
OPCR[3:2]—OP3 Output Select
This bit programs the OP3 output to provide one of the following:
00
The complement of OPR[3].
01
The counter/timer output, in which case OP3 acts as an
open-drain output. In the timer mode, this output is a square
wave at the programmed frequency. In the counter mode,
the output remains High until terminal count is reached, at
which time it goes Low. The output returns to the High state
when the counter is stopped by a stop counter command.
Note that this output is not masked by the contents of the
IMR.
10
The 1X clock for the Channel B transmitter, which is the
clock that shifts the transmitted data. If data is not being
transmitted, a free running 1X clock is output.
11
The 1X clock for the Channel B receiver, which is the clock
that samples the received data. If data is not being received,
a free running 1X clock is output.
OPCR[1:0]—OP2 Output Select
This field programs the OP2 output to provide one of the following:
00
The complement of OPR[2].
01
The 16X clock for the Channel A transmitter. This is the
clock selected by CSRA[3:0], and will be a 1X clock if
CSRA[3:0] = 1111.
10
The 1X clock for the Channel A transmitter, which is the
clock that shifts the transmitted data. If data is not being
transmitted, a free running 1X clock is output.
11
The 1X clock for the Channel A receiver, which is the clock
that samples the received data. If data is not being received,
a free running 1X clock is output.
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