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參數(shù)資料
| 型號： | 935262756118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | AHC SERIES, 2-INPUT OR GATE, PDSO5 |
| 封裝： | PLASTIC, SC-88A, 5 PIN |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 74K |
| 代理商： | 935262756118 |
2002 Jun 05
2
Philips Semiconductors
Product specication
2-input OR gate
74AHC1G32; 74AHCT1G32
FEATURES
Symmetrical output impedance
High noise immunity
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
Low power dissipation
Balanced propagation delays
Multiple very small 5-pin packages
Output capability: standard
Specified from 40 to +125 °C.
DESCRIPTION
The 74AHC1G/AHCT1G32 is a high-speed Si-gate CMOS
device.
The 74AHC1G/AHCT1G32 provides the 2-input
OR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC1G
AHCT1G
tPHL/tPLH
propagation delay A and B to Y CL = 15 pF; VCC = 5 V
3.2
3.3
ns
CI
input capacitance
1.5
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
16
17
pF
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