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參數(shù)資料
| 型號(hào)： | 935262436118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 147K |
| 代理商： | 935262436118 |
December 1990
9
Philips Semiconductors
Product specication
Presettable synchronous BCD decade
counter; asynchronous reset
74HC/HCT160
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min. typ.
max.
min.
max.
min.
max.
tPHL/ tPLH propagation delay
CP to Qn
25
43
54
65
ns
4.5
Fig. 8
tPHL
propagation delay
CP to TC
28
48
60
72
ns
4.5
Fig. 8
tPLH
propagation delay
CP to TC
23
39
49
59
ns
4.5
Fig. 8
tPHL
propagation delay
MR to Qn
27
50
63
75
ns
4.5
Fig. 9
tPHL
propagation delay
MR to TC
30
50
63
75
ns
4.5
Fig. 9
tPHL
propagation delay
CET to TC
17
35
44
53
ns
4.5
Fig. 10
tPLH
propagation delay
CET to TC
9
17
21
26
ns
4.5
Fig. 10
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Figs 8 and 10
tW
clock pulse width
HIGH or LOW
16
8
20
24
ns
4.5
Fig. 8
tW
master reset pulse width
LOW
20
11
25
30
ns
4.5
Fig. 9
trem
removal time
MR to CP
20
9
25
30
ns
4.5
Fig. 9
tsu
set-up time
Dn to CP
18
10
25
30
ns
4.5
Fig. 11
tsu
set-up time
PE to CP
30
18
44
53
ns
4.5
Fig. 11
tsu
set-up time
CEP, CET to CP
50
30
63
75
ns
4.5
Fig. 12
th
hold time
Dn to CP
0
8
0
ns
4.5
Figs 11 and 12
th
hold time
PE to CP
0
13
0
ns
4.5
Figs 11 and 12
th
hold time
CEP, CET to CP
0
21
0
ns
4.5
Figs 11 and 12
fmax
maximum clock pulse
frequency
16
28
13
11
MHz
4.5
Fig. 8
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