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參數(shù)資料
| 型號(hào)： | 935206130112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | OT PLD, 35 ns, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 935206130112 |
Philips
Semiconductors
Product
specification
PLC18V8Z
Zero
standby
power
CMOS
versatile
P
AL
devices
1997
Aug
08
16
*
THE
CONFIGURA
TION
CELL
IS
AUT
OMA
TICALL
Y
PROGRAMMED
BASED
ON
THE
OMC
ARCHITECTURE.
**
FOR
SP
,AR:
“
–
”
IS
NOT
ALLOWED.
T
E
R
M
7654321
0
765432
10
7654
3210
8
9
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
SP
AR
PIN
D
A
D
A
D
A
D
A
D
A
D
A
D
A
D
A
1
98765
4321
1
2
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
VARIABLE
NAME
AND
OR
(FIXED)
CONFIGURA
TION
CELL
(CLK/OE
CONTROL)
I
F
(I)
F
(B,
O,
D)
ARCH.
CONTROL
BITS
OUTPUT
POLARITY
CUSTOMER NAME
PURCHASE ORDER #
PHILIPS DEVICE #
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
PROGRAM TABLE #
REV.
DATE
NOTES:
In the unprogrammed or virgin state:
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
Pins 1 and 11 are configured as inputs 0 and 9, respectively, via
the configuration cell. The clock and OE functions are disabled.
All output macro cells (OMC) are configured as combinatorial I/O,
with the outputs disabled via the direction control term.
INACTIVE
I,F
(I,
B)
I,F
(I,
B)
**DON’T
CARE
O
H
L
–
AND
ARRA
Y
CONTROL
OR
ARRA
Y
(FIXED)
REGISTERED
(D-TYPE)
FIXED
INPUT
FIXED
OUTPUT
BIDIRECTIONAL
I/O
D
I
O
B
OMC
ARCH.
OUTPUT
POLARITY
NON-INVERTING
INVERTING
H
L
CONFIG.
CELL*
PIN
1
=
CLK;
PIN
1
1=
OE
PIN
1,
PIN
1
1=
INPUT
L
H
DA
TA
CANNOT
BE
ENTERED
INT
O
THE
OR
ARRA
Y
FIELD
DUE
T
O
THE
FIXED
NA
TURE
OF
THE
DEVICE
ARCHITEC-
TURE.
DIRECTION
CONTROL
ACTIVE
OUTPUT
D
A
NOT
USED
PROGRAM
T
ABLE
SP00029
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