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參數(shù)資料
| 型號(hào)： | 935167440557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 46/112頁 |
| 文件大?。?/td> | 707K |
| 代理商： | 935167440557 |
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1996 Jun 27
39
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
Notes to the description of the SR bits
1. When the Bus Status bit is set HIGH (Bus-OFF), the CAN-controller will set the Reset Request bit HIGH (present).
It will stay in this state until the CPU sets the Reset Request bit LOW (absent). Once this is completed the
CAN-controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) before setting
the Bus Status bit LOW (Bus-ON), the Error Status bit LOW (ok) and resetting the Error Counters. During Bus-OFF
the output drivers are switched off (floating); external transceiver circuits should output a recessive level in this case.
2. If both the Receive Status and Transmit Status bits are LOW (idle) the CAN-bus is idle.
3. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Access bit is LOW (locked), the written bytes
will not be accepted and will be lost without this being signalled. The Transmission Complete Status bit is set LOW
(incomplete) whenever the Transmission Request bit is set HIGH (present). If an Abort Transmission command is
issued, the Transmit Buffer will be released. If the message, which was requested and then aborted, was not
transmitted, the Transmission Complete Status bit will remain LOW.
4. If Data Overrun = HIGH (overrun) is detected, the currently received message is dropped. A transmitted message,
granted acceptance, is also stored in a Receive Buffer. This occurs because it is not known if the CAN-controller will
lose arbitration and so become a receiver of the message. If no Receive Buffer is available, Data Overrun is
signalled. However, this transmitted and accepted message does neither cause a Receive Interrupt nor set the
Receive Buffer Status bit to HIGH (full). Also, a Data Overrun does not cause the transmission of an Overload Frame
(see Sections 13.6.1 and 13.6.5).
5. If the command bit Release Receive Buffer is set HIGH (released) by the CPU, the Receive Buffer Status bit is set
LOW (empty) by IML. When a new message is stored in any of the receive buffers, the Receive Buffer Status bit is
set HIGH (full) again.
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