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1998 Sep 08
27
Philips Semiconductors
Product specication
LCD row/column driver for dot matrix
graphic displays
PCF8578
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS =0V; VLCD =VDD 3.5 V to VDD 9V;Tamb = 40 to +85 °C; unless otherwise specied.
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD <VPOR.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V2 to V5, VDD and VLCD) when the specified current flows through one output under the following conditions
(see Table 2):
a) Vop =VDD VLCD =9V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 VLCD ≥ 6.65 V; V5 VLCD ≤ 2.35 V; ILOAD = 150 A.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 VLCD ≥ 4.70 V; V4 VLCD ≤ 4.30 V; ILOAD = 100 A.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
6.0
V
VLCD
LCD supply voltage
VDD 9
VDD 3.5 V
IDD1
supply current external clock
fCLK = 2 kHz; note 1
615
A
IDD2
supply current internal clock
ROSC = 330 k
20
50
A
VPOR
power-on reset level
note 2
0.8
1.3
1.8
V
Logic
VIL
LOW level input voltage
VSS
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
VDD
V
IOL1
LOW level output current at SYNC
and CLK
VOL =1V; VDD =5V
1
mA
IOH1
HIGH level output current at SYNC
and CLK
VOH =4V; VDD =5V
1mA
IOL2
LOW level output current at SDA
VOL = 0.4 V; VDD =5V
3
mA
IL1
leakage current at SDA, SCL, SYNC,
CLK, TEST and SA0
Vi =VDD or VSS
+1
mA
IL2
leakage current at OSC
Vi =VDD
+1
A
Ci
input capacitance at SCL and SDA
note 3
5pF
LCD outputs
IL3
leakage current at V2 to V5
Vi =VDD or VLCD
2
+2
A
VDC
DC component of LCD drivers
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
±20
mV
RROW
output resistance R0 to R7 and
R8/C8 to R31/C31
row mode; note 4
1.5
3
k
RCOL
output resistance R8/C8 to R31/C31
and C32 to C39
column mode; note 4
36
k