參數(shù)資料
型號： 935026970623
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 115.2K bps, SERIAL COMM CONTROLLER, PQCC28
封裝： PEDESTAL, PLASTIC, MO-047AB, SOT-261-3, LCC-28
文件頁數(shù)： 18/28頁
文件大?。?/td> 264K
代理商： 935026970623
Philips Semiconductors - PIP - SCC2691; Universal asynchronous receiver/transmitter (UART)
Product Information
SCC2691; Universal
asynchronous
receiver/transmitter
(UART)
Information as of 2003-04-22
Stay informed
Download datasheet
Block diagram
topGeneral description
The Philips Semiconductors SCC2691 Universal Asynchronous Receiver/Transmitter (UART) is a single-chip CMOS-LSI
communications device that provides a full-duplex asynchronous receiver/transmitter. It is fabricated with Philips
Semiconductors CMOS technology which combines the benefits of high density and low power consumption.
The operating speed of the receiver and transmitter can be selected independently as one of 18 fixed baud rates, a 16X
clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the
operating speed of the receiver and transmitter make the UART particularly attractive for dual-speed channel applications
such as clustered terminal systems.
The receiver is quadruple buffered to minimize the potential of receiver overrun or to reduce interrupt overhead in interrupt
driven systems. In addition, a handshaking capability is provided to disable a remote UART transmitter when the receiver
buffer is full.
The UART provides a power-down mode in which the oscillator is frozen but the register contents are stored. This results
in reduced power consumption on the order of several magnitudes.
The UART is fully TTL compatible and operates from a single +5V power supply.
topFeatures
q
Full-duplex asynchronous receiver/transmitter
q
Quadruple buffered receiver data register
q
Programmable data format:
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
q
16-bit programmable Counter/Timer
q
Baud rate for the receiver and transmitter selectable from:
– 22 fixed rates: 50 to 115.2K baud
– Non-standard rates to 115.2kb
– Non-standard user-defined rate derived from programmable timer/ counter
– External 1X or 16X clock
q
Parity, framing, and overrun detection
q
False start bit detection
q
Line break detection and generation
q
Programmable channel mode
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/SCC2691AC1N24.html (1 of 4) [Apr-30-2003 2:11:33 PM]
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