參數(shù)資料
型號(hào)： 935014090005
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC54
封裝： DIE-54
文件頁(yè)數(shù)： 6/46頁(yè)
文件大?。?/td> 287K
代理商： 935014090005
1998 Sep 08
14
Philips Semiconductors
Product specication
LCD row/column driver for dot matrix
graphic displays
PCF8578
7.5
Internal clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor ROSC, see Fig.9.
For normal use a value of 330 k
is recommended.
The clock signal, for cascaded PCF8579s, is output at CLK
and has a frequency 1
6 (multiplex rate 1 : 8, 1 : 16 and
1 : 32) or 1
8 (multiplex rate 1 : 24) of the oscillator
frequency.
Fig.9
Oscillator frequency as a function of
external oscillator resistor, ROSC.
To avoid capacitive coupling, which could adversely affect oscillator
stability, ROSC should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to ROSC.
10
MSA837
102
103
104
1
10 3
10
10 2
f OSC
(kHz)
R(k
)
OSC
7.6
External clock
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7
Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8
Row/column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
Table 4
Signal frequencies required for nominal 64 Hz frame frequency; note 1.
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. ROSC = 330 k.
OSCILLATOR
FREQUENCY
fOSC(2) (Hz)
FRAME FREQUENCY
fSYNC (Hz)
MULTIPLEX RATE (n)
DIVISION
RATIO
CLOCK FREQUENCY
fCLK (Hz)
12288
64
1 : 8, 1 : 16, 1 : 32
6
2048
12288
64
1 : 24
8
1536
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