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參數(shù)資料
| 型號： | 935002730512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 115.2K bps, SERIAL COMM CONTROLLER, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 264K |
| 代理商： | 935002730512 |
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Philips Semiconductors
Product specification
SCC2691
Universal asynchronous receiver/transmitter (UART)
1998 Sep 04
16
RDN
MPI
WRN
MPO
tPS
tPH
tPD
SD00125
Figure 5. I/O Timing
WRN
INTERRUPT1
OUTPUT
RDN
INTERRUPT1
OUTPUT
VM
tIR
VOL +0.5V
VOL
NOTES:
1. INTRN or MPO when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal,
VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment
are pronounced and can greatly affect the resultant measurement.
SD00126
Figure 6. Interrupt Timing
X1/CLK
C/T CLK
RxC
TxC
tCLK
tCTC
tRx
tTx
tCLK
tCTC
tRx
tTx
C1
C2
Y1
X1/CLK
X2
SCC2691
Y1 = 3.6864MHz, CL = 20pF
C1 = C2 = 24pF
CLK
5V
470
X1
X2
N/C
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY. . . . . . . . . . . . . . 2–4MHz
LOAD CAPACITANCE (CL). . . 20 or 32pF (typical)
TYPE OF OPERATION . . . . . .PARALLEL RESONANT, FUND. MODE
DRIVING
FROM EXTERNAL
SOURCE
50k
to
150k
SD00127
Figure 7. Clock Timing
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